The present invention relates to integrated circuits and to methods for manufacturing them.
In a new class of integrated circuit fabrication processes taught by the grandparent application (Ser. No. 729,318, filed 05/01/85, a very novel local interconnect technology was set forth, which resulted in very conveniently produced titanium nitride local interconnect line. These lines can be routed to interconnect p+ substrate regions, n+ substrate regions, and polysilicon in any pattern desired, while also permitting self-aligned silicidation to occur to clad surfaces of exposed silicon substrate areas and also of exposed polysilicon lines with silicide, to improve their conductivity.
In conventional processes for making dynamic random-access memories (DRAMs), the memory cells are formed using two separate polysilicon layers. The first layer is typically used for the gate of the pass transistor, and the second layer is typically used for the top plate of the storage capacitor.
Since thin film deposition steps and patterned etching steps are both significantly expensive process steps, it would be highly desirable to be able to fabricate such devices with a reduced number of polysilicon deposition and etching steps. This would provide reduced fabrication cost, which is most especially important in such "commodity" parts.
The present invention teaches that, as a particularly useful development of the technology taught in the grandparent application, titanium nitride formation can be used to drastically simplify the structure and fabrication of many structures which normally require two levels of polysilicon, and in particular of DRAM memory structures. The present invention teaches that a DRAM memory can be built using only one layer of deposited polysilicon. A patterned dielectric covers some areas of the polysilicon, so that the titanium metal in these areas does not form silicides during the reaction process, but will be converted to a thin film of titanium nitride, which is a very convenient conductor. However, where underlying silicon areas (either of substrate monocrystalline silicon or of polycrystalline silicon) were not protected by this thin dielectric from the deposited titanium, the nitrogen-atmosphere reaction step will form titanium silicide at all such locations. Wherever the titanium metal runs over field oxide or over other non-silicon materials, it will form titanium nitride. This titanium nitride will already be in ohmic contact with any area of exposed silicon it runs over. Thus, simply by patterning this titanium nitride layer, the equivalent of a second polysilicon layer with full buried contact capability is achieved. That is, this layer can make direct contact to n+ or p+ source/drain portions of the substrate wherever (in the periphery) is desired.
Thus, the present invention offers the significant advantage of simpler processing than conventional DRAM memory fabrication methods.
The present invention offers the further advantage that the titanium nitride layer is typically thinner than the second polysilicon layer which can be left out of the process because of the presence of titanium nitride. That is, the bulk resistivity of titanium nitride is low enough that acceptable sheet resistance (for short interconnects) can be achieved for a relatively thin film of TiN (10.OMEGA./.quadrature. or better for a 1000 Angstrom thick TiN film).
The present invention offers yet a further advantage in that the diffusion barrier characteristics of TiN permit this layer to make contacts directly to n+ or p+ silicon or polysilicon, without any problems due to diffusion of dopants through the TiN interconnect to induce counterdoping. This is not the case, for example, with silicides in general.
The present invention also provides an improved capacitor structure, which may be useful, for example, in bootstrapping circuits as well as for storage capacitors of memory cells art. One class of embodiments of the present invention teaches that a single layer containing silicon--in particular, a single layer which consists essentially of silicon at its bottom boundary, to provide the advantageous electrical properties of a silicon/dielectric interface--is used for the bottom plate of capacitors, and also for the gates of insulated gate field effect transistors. A titanium nitride thin film interconnect layer is used for the top plates of capacitors, and preferably also for local interconnect. The portions of the thin film titanium nitride layer which are used for local interconnect can link polysilicon, silicides, and crystalline silicon of any dopant level in any pattern desired. Again, this innovation provides improved topography and also simpler fabrication, resulting in higher yield and lower cost.
Another advantageous use of the TiN layer is to provide pads at the bottom of contact holes. Since the oxide etch chemistries normally used for contact etching are somewhat selective to TiN this layer provides some protection against overetching when the contact etch step must etch contact holes of various thicknesses. In particular, the present invention makes it easier to etch contact holes to substrate and to the polysilicon layer simultaneously. Moreover, the TiN etch stop pads can be extended from the source/drain regions (in the moats) up onto the field oxide so that the contact hole does not have to fall within the perimeter of the source/drain, but can overlap up onto the field oxide. This means that the source/drain patterns can be drawn smaller, providing a further advantage of the invention.
Yet another use of the TiN layer provided by the presently preferred embodiments of the present invention is to provide capacitors to substrate. Since the interlevel dielectric is patterned after the source/drain implants, these capacitors can be located over heavily doped diffusions, so their parasitic series resistance should not be large.
Yet another use of the TiN layer provided by the presently preferred embodiments of the present invention is to provide Schottky diodes to substrate. By screening the source/drain implant from some areas of bare silicon, the TiSi.sub.2 /TiN layer formed on these areas will provide usable Schottky diodes.
Thus, the present invention provides a DRAM cell which can be fabricated by a much simpler process than is conventionally used, with no degradation in device performance. In some embodiments, this DRAM cell also is more nearly planar than the cells of the prior art, which further increases the yield by decreasing the risk in subsequent process steps; e.g., there is less danger of filaments when the metal level is etched.
According to the present invention there is provided: An integrated circuit memory comprising: a substrate, including device isolation regions defining moat areas of exposed semiconducting material; a plurality of memory cells, each said cell comprising an insulated-gate field effect pass transistor having a channel and first and second source/drains in a respective one of said moat areas, and a storage capacitor having a lower plate a capacitor dielectric and an upper plate insulated from said lower plate by a capacitor dielectric, said plates substantially overlying said device isolation regions, said first source/drain of said pass transistor being connected through a local interconnect to said upper plate of said storage capacitor; said gates of ones of said pass transistors and said bottom plates of ones of said capacitors comprising respective portions of a first patterned thin film conductive layer which is polycrystalline and comprises more than 30% atomic of silicon; said local interconnects and said top plates of ones of said capacitors comprising respective portions of a second patterned thin film conductive layer consisting predominantly of titanium nitride; at least one bitline connected to respective ones of said second source/drains of said pass transistors; and at least one wordline connected to respective ones of said gates of said pass transistors.
According to the present invention there is also provided: An integrated circuit memory comprising: a substrate including areas of crystalline semiconducting material; a plurality of memory cells, each said cell comprising an insulated-gate field effect pass transistor having a channel and first and second source/drains in said semiconducting material, and a storage capacitor having a lower plate, a capacitor dielectric, and an upper plate insulated from said lower plate by a capacitor dielectric, said bottom plate overlying said semiconducting material and being separated therefrom by a field plate dielectric, said first source/drain of said pass transistor being connected through a local interconnect to said upper plate of said storage capacitor; said gates of ones of said pass transistors and said bottom plates of ones of said capacitors comprising respective portions of a first patterned thin film conductive layer which is polycrystalline and comprises more than 30% atomic of silicon; said local interconnects and said top plates of ones of said capacitors comprising respective portions of a second patterned thin film conductive layer consisting predominantly of titanium nitride; at least one bitline connected to respective ones of said second source/drains of said pass transistors; and at least one wordline connected to respective ones of said gates of said pass transistors.